Copper interconnect technology has been widely adopted for advanced high performance integrated circuit devices. Because copper (Cu) has a higher melting point than aluminum, it was expected that Cu would have improved current carrying capability and extended electro-migration lifetime. Conventionally, Cu metallization is formed by depositing a thin barrier metal layer, e.g., formed of tantalum-nitrate and tantalum (TaN/Ta), in the trenches or vias formed in dielectric layers by dry etching. A thin Cu metal seed layer then covers the barrier layer. The Cu seed layer is needed for subsequent electroplating of a Cu layer in order to completely fill the vias and trenches of the dielectric layers. Any overplated Cu layers are chemical mechanically polished back to leave Cu metallization in the trenches and vias. This Cu metallization process is repeated several times to form multi-layered circuits. For example, multiple dielectric layers with Cu metallization are typically stacked on top of a semiconductor wafer substrate. Each of the dielectric layers and corresponding Cu metallization are referred to as a “metal layer.” The metal layers provide for electrical interconnectivity between integrated circuits within the semiconductor wafer substrate.
Although a proven technology, the tri-layer deposition of TaN/Ta—Cu does not scale well below 65 nm technology where a high resistance TaN/Ta barrier layer starts to occupy a greater fraction of conductor volume. In addition, deposition of Cu seed layers typically result in a relatively thick metal layer overhang near the opening of vias and trenches that prevent successful void free Cu electroplating in smaller features. Furthermore, the tri-layer deposition requires deposition in two separate processing (e.g., deposition) chambers and hence incurs higher production cost in terms of tool capital expenditure and yield loss. Cu may be deposited with various deposition techniques, such as sputtering and chemical vapor deposition. Therefore, efforts have been devoted to develop a direct Cu plate-able single layer barrier layer for future Cu interconnect technology.
Currently, ruthenium (Ru) is a leading candidate since it is an air stable transition metal with a high melting point (2310° C.) and is nearly twice as electrically conductive (7.6 uOhm-cm) as Ta (12.5 uOhm-cm). In addition, Ru, like Ta, shows negligible solubility with Cu even at 900° C. based on a binary phase diagram. Furthermore, researchers have demonstrated that it is possible to directly electroplate Cu over a very thin layer of Ru, e.g., less than 10 nm, and hence eliminate the need to deposit a so-called seed layer. Such a scheme, if implemented, would provide a significant increase in electrical performance while reducing the production cost by one-half (e.g., saving in tool cost and increase in yield).
Unfortunately, Ru is not a good barrier layer for Cu because it does not react with nitrogen to form an effective barrier layer. Normally, a metal nitride, if conductive, would be a better choice as a copper diffusion barrier than it's metal counterpart due to increased atomic packing density and inert nature. The maximum temperature before copper diffusion through Ru into silicon oxide is only 450° C., which is considerable inferior to TaN (at approximately >700° C.).
In view of the foregoing, there are continuing efforts to provide improved techniques for forming barrier and seed layers in semiconductor metallization processes.